Method and system for gallium nitride electronic devices using engineered substrates

ABSTRACT

A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.13/572,408, filed on Aug. 10, 2012, the disclosure of which is herebyincorporated by reference in its entirety for all purposes.

BACKGROUND OF THE INVENTION

Power electronics are widely used in a variety of applications. Powerelectronic devices are commonly used in circuits to modify the form ofelectrical energy, for example, from ac to dc, from one voltage level toanother, or in some other way. Such devices can operate over a widerange of power levels, from milliwatts in mobile devices to hundreds ofmegawatts in a high voltage power transmission system. Despite theprogress made in power electronics, there is a need in the art forimproved electronics systems and methods of operating the same.

SUMMARY OF THE INVENTION

The present invention relates generally to electronic devices. Morespecifically, the present invention relates to devices fabricating usingengineered substrates to provide improvements in device performanceparameters. The methods and techniques can be applied to a variety ofcompound semiconductor systems including vertical junction field effecttransistors (JFETs), electrical contact structures, diode structures,and the like.

According to an embodiment of the present invention, a method forfabricating an electronic device is provided. The method includesproviding an engineered substrate structure comprising a III-nitrideseed layer, forming GaN-based functional layers coupled to theIII-nitride seed layer, and forming a first electrode structureelectrically coupled to at least a portion of the GaN-based functionallayers. The method also includes joining a carrier substrate opposingthe GaN-based functional layers and removing at least a portion of theengineered substrate structure. The method further includes forming asecond electrode structure electrically coupled to at least anotherportion of the GaN-based functional layers and removing the carriersubstrate.

According to another embodiment of the present invention, a verticalIII-nitride electronic device is provided. The device includes a firstelectrical contact structure and a III-nitride epitaxial layer of afirst conductivity type coupled to the first electrical contactstructure. The device also includes a III-nitride epitaxial structurecoupled to the III-nitride epitaxial layer and a second electricalcontact structure coupled to one or more layers of the III-nitrideepitaxial structure.

According to an alternative embodiment of the present invention, avertical III-nitride JFET is provided. The vertical III-nitride JFETincludes a device substrate, an interface layer coupled to the devicesubstrate, and a first electrode structure coupled to the interfacelayer. The vertical III-nitride JFET also includes a III-nitrideepitaxial layer connected to the first electrode structure, aIII-nitride drift layer epitaxially coupled to the III-nitride epitaxiallayer, and a III-nitride channel region epitaxially coupled to theIII-nitride drift layer. The vertical III-nitride JFET further includesa III-nitride source region epitaxially coupled to the III-nitridechannel region and one or more gate regions disposed adjacent theIII-nitride channel region.

Numerous benefits are achieved by way of the present invention overconventional techniques. For example, embodiments of the presentinvention utilize an engineered substrate during the fabrication of highpower, vertical GaN-based devices such as vertical FETs. The use of theengineered substrate results in cost reduction in some embodiments.Additionally, some embodiments are characterized by reduced substratethinning and/or removal processes. For some vertical devices,particularly, high performance GaN-based devices, the substrateresistance is substantial and can impact device performance. In order toreduce resistance associated with the substrate, portions or all of thesubstrate can be thinned/removed after initial processing. Embodimentsof the present invention utilize engineered substrates withpredetermined GaN-based epitaxial layers that provide desired devicecharacteristics after the handle substrate and bonding layers have beenremoved. These and other embodiments of the invention, along with manyof its advantages and features, are described in more detail inconjunction with the text below and attached figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified cross-sectional diagram illustrating anengineered substrate according to an embodiment of the presentinvention;

FIG. 2 is a simplified cross-sectional diagram illustrating epitaxialgrowth on the engineered substrate according to an embodiment of thepresent invention;

FIG. 3 is a simplified cross-sectional diagram illustrating formation ofan electrode according to an embodiment of the present invention;

FIG. 4 is a simplified cross-sectional diagram illustrating joining of acarrier wafer according to an embodiment of the present invention;

FIG. 5 is a simplified cross-sectional diagram illustrating thinning ofthe handle wafer according to an embodiment of the present invention;

FIG. 6 is a simplified cross-sectional diagram illustrating removal oflayers and formation of an electrode according to an embodiment of thepresent invention;

FIG. 7 is a simplified cross-sectional diagram illustrating joining of asubstrate according to an embodiment of the present invention;

FIG. 8 is a simplified cross-sectional diagram illustrating removal ofthe carrier wafer according to an embodiment of the present invention;

FIG. 9A is a simplified schematic diagram of a GaN Schottky diodestructure according to an embodiment of the present invention;

FIG. 9B is a simplified schematic diagram of a GaN p-n diode structureaccording to an embodiment of the present invention;

FIG. 10 is a simplified schematic diagram of a three-terminal GaN FETstructure according to an embodiment of the present invention;

FIG. 11 is a simplified schematic diagram of a three-terminal GaNbipolar structure according to an embodiment of the present invention;

FIG. 12 is a simplified schematic diagram illustrating device bondingaccording to an embodiment of the present invention; and

FIG. 13 is a simplified flowchart illustrating a method of fabricatingan electronic device according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Embodiments of the present invention relate to electronic devices. Morespecifically, the present invention relates to devices fabricating usingengineered substrates to provide improvements in device performanceparameters. The methods and techniques can be applied to a variety ofcompound semiconductor systems including vertical junction field effecttransistors (JFETs), electrical contact structures, diode structures,and the like.

GaN-based electronic and optoelectronic devices are undergoing rapiddevelopment. Desirable properties associated with GaN and related alloysand heterostructures include high bandgap energy for visible andultraviolet light emission, favorable transport properties (e.g., highelectron mobility and saturation velocity), a high breakdown field, andhigh thermal conductivity. According to embodiments of the presentinvention, gallium nitride (GaN) epitaxy on GaN seed layers formed onengineered substrates is utilized to fabricate vertical GaN-basedsemiconductor devices not possible using conventional techniques. Forexample, conventional methods of growing GaN include using a foreignsubstrate such as silicon carbide (SiC). This can limit the thickness ofa usable GaN layer grown on the foreign substrate due to differences inthermal expansion coefficients and lattice constant between the GaNlayer and the foreign substrate. High defect densities at the interfacebetween GaN and the foreign substrate further complicate attempts tocreate vertical devices, including power electronic devices such asJFETs and other field-effect transistors.

Homoepitaxial GaN layers on GaN seed layers, on the other hand, areutilized in the embodiments described herein to provide superiorproperties to conventional techniques and devices. For instance,electron mobility, μ, is higher for a given background doping level, N.This provides low resistivity, ρ, because resistivity is inverselyproportional to electron mobility, as provided by equation (1):

$\begin{matrix}{{\rho = \frac{1}{q\; \mu \; N}},} & (1)\end{matrix}$

where q is the elementary charge.

Another superior property provided by homoepitaxial GaN layers on GaNseed layers is high critical electric field for avalanche breakdown. Ahigh critical electric field allows a larger voltage to be supportedover smaller length, L, than a material with a lower critical electricfield. A smaller length for current to flow together with lowresistivity give rise to a lower resistance, R, than other materials,since resistance can be determined by the equation:

$\begin{matrix}{{R = \frac{\rho \; L}{A}},} & (2)\end{matrix}$

where A is the cross-sectional area of the channel or current path.

In general, a tradeoff exists between the physical dimension of a deviceneeded to support high voltage in a device's off-state and the abilityto pass current through the same device with low resistance in theon-state. In many cases GaN is preferable over other materials inminimizing this tradeoff and maximizing performance. In addition, GaNlayers grown on GaN seed layers on engineered substrates have low defectdensity compared to layers grown on mismatched substrates. The lowdefect density will give rise to superior thermal conductivity, lesstrap-related effects such as dynamic on-resistance, and betterreliability.

Among the vertical device structures contemplated is a vertical JFET.Depending on doping levels, physical dimensions, conductivity type(e.g., n-type or p-type materials), and other factors, vertical JFETscan be designed to have normally-off or normally-on functionality. Anormally-off vertical JFET is particularly useful due to its ability toprevent current flow if no voltage is applied to the gate, which canserve as, among other things, a safety feature for vertical JFETs usedin power applications.

A normally-off vertical JFET can be created in various ways. Forexample, an n-type current path from source to drain can be gated oneither side by p+ gates. With sufficiently low background doping, andhigh positive charge due to high hole concentration in the p+ gates, thechannel can be depleted of carriers, or pinched off at zero bias. When apositive voltage is applied to the gate(s), the channel can be re-openedto turn the device on. Thus, in embodiments of the present invention,the vertical JFET is referred to as a vertical junction field effecttransistor since the current flows vertically between the source anddrain through the gated region.

In addition to the ability to support high-voltage, low-resistance JFETapplications, the GaN vertical JFETs described herein can differ fromtraditional vertical JFETs in other ways. For example, othersemiconductors used to manufacture vertical JFETs, such as SiC can beutilized, altering the mode of manufacture. Furthermore, the use of GaNepitaxial layers can allow for non-uniform dopant concentrations as afunction of thickness within the various layers of the vertical JFET,which can optimize the performance of the device.

FIG. 1 is a simplified cross-sectional diagram illustrating anengineered substrate 10 according to an embodiment of the presentinvention. As illustrated in FIG. 1, the engineered substrate 10includes a handle substrate 100, a bonding layer 101, and a GaN-basedseed layer 102. In one embodiment, the bonding layer 101 is an oxidelayer, but, as described more fully below, this is not required byembodiments of the present invention.

The handle substrate 100 provides mechanical rigidity to supportoverlying layers during handling and processing operations and can bemade of a single material or combinations of materials in either alaminated structure, an alloy structure, or combinations thereof. As anexample, the handle substrate can include metal materials, ceramicmaterials, semiconductor materials, or combinations thereof. As will beevident to one of skill in the art, the engineered substrate 10 sharessome common features with silicon-on-insulator substrates used insilicon-based applications. The GaN seed layer 102 is epitaxially liftedoff in some embodiments during the fabrication of the engineeredsubstrate 10. In other embodiments, the GaN seed layer is a portion of aGaN substrate that is bonded to the bonding layer 101 and then split offfrom the substrate using a layer transfer process. One of ordinary skillin the art would recognize many variations, modifications, andalternatives.

The engineered substrate 10 can be utilized, as described herein, in thefabrication of high-power GaN-based electronic devices, providing costreductions in comparison with conventional techniques, reducingprocessing related to thinning and removal of GaN-based substratematerials, and the like.

FIG. 2 is a simplified cross-sectional diagram illustrating epitaxialgrowth on the engineered substrate according to an embodiment of thepresent invention. As illustrated in FIG. 2, a buffer layer 201 (e.g.,an n+ GaN buffer layer) is formed, for example, using a metalorganicchemical vapor deposition (MOCVD) process on the GaN-based seed layer102. In the illustrated embodiment, the buffer layer is heavily dopedn-type to form a highly conductive N+ layer since the seed layer can behighly resistive. For example, layer 201 may be doped with silicon oroxygen to a dopant concentration in the range of 1×10¹⁷ cm⁻³ to 1×10²⁰cm⁻³ and have a thickness in the range of 0.1 μam to 10 μm. A driftlayer 301 (e.g., an n-type GaN drift layer), which forms an element of avertical electronic device, is then formed on the buffer layer 201.Other functional layers 401 are then formed on the drift layer 301 andare intended to represent a wide variety of functional layers asappropriate to particular applications.

In some embodiments, after fabrication, the buffer layer 201 will serveas an n-type contact layer and the drift layer 301 will provide devicefunctionality appropriate, for example, for a vertical JFET. Theproperties of drift layer 301 can vary, depending on desiredfunctionality. For example, to support high voltages, layer 301 can be arelatively low-doped material with sufficient thickness. In someembodiments, the dopant concentration of layer 301 is substantiallylower than the dopant concentration of layer 201. For example, layer 301can have an n− conductivity type, with dopant concentrations rangingfrom 1×10¹⁴ cm⁻³ to 1×10¹⁸ cm⁻³. Furthermore, the dopant concentrationcan be uniform, or can vary, for example, as a function of the thicknessof the drift region. The thickness of layer 301 may be in the range of 4μm to 100 μm, depending on the target voltage rating. In someembodiments, layer 301 can comprise two or more sublayers, which canhave differing physical characteristics (e.g., dopant concentrations,dopant uniformity, etc.).

Referring to FIGS. 1 and 2, GaN seed layer 102 may be substantiallyundoped, compensation-doped (i.e. have substantially equalconcentrations of n-type and p-type doping, such that the net dopingconcentration is small), or may have net n-type doping or net p-typedoping. Additionally, although a GaN seed layer is illustrated in FIGS.1 and 2, embodiments of the present invention are not limited to GaNseed layers. Other III-V materials, in particular, III-nitridematerials, are included within the scope of the present invention andcan be substituted not only for the illustrated GaN seed layer, but alsofor other GaN-based layers and structures described herein. As examples,binary III-V (e.g., III-nitride) materials, ternary III-V (e.g.,III-nitride) materials such as InGaN and AlGaN, quaternary III-nitridematerials, such as AlInGaN, doped versions of these materials, and thelike are included within the scope of the present invention.

FIG. 3 is a simplified cross-sectional diagram illustrating formation ofan electrode according to an embodiment of the present invention. A topelectrode 501 is electrically connected to one or more of the otherapplicable functional layers 401 and the actual design and integrationwill depend on the particular device design and functionality providedby the particular device. As an example, the top electrode 501 can beformed from one or more layers of electrical conductors including avariety of metals to electrically couple the top electrode 501 to anelectrical circuit (not illustrated).

FIG. 4 is a simplified cross-sectional diagram illustrating joining of acarrier wafer according to an embodiment of the present invention.Referring to FIG. 4, a sacrificial bonding layer 601 is joined to thetop electrode 501 and portions of the other applicable functional layers401 and provides mechanical support for the bonding of carrier wafer 701to the material structure. As described more fully below, the carrierwafer 701 will enable subsequent processing to be used to remove thehandle wafer and other suitable layers. One of ordinary skill in the artwould recognize many variations, modifications, and alternatives.

In an embodiment, the material used to form the sacrificial bondinglayer 601 can include wax, an oxide material, an organic tape, otherorganic or metallic materials suitable for bonding of the carrier wafer701, combinations thereof, or the like. Typically, the sacrificialbonding layer 601 is a fairly soft material that is easily removed andprovides for resistance to chemical attack during subsequent processing.In general, the sacrificial bonding layer 601 will be selected in lightof the particular materials used for the carrier wafer in order toprovide a good match to the carrier wafer. Thus, the sacrificial bondinglayer 601 provides both adhesion and chemical resistance.

The material used to form the carrier wafer 701 can include rigidsubstrates such as sapphire, silicon carbide, silicon, and the like, orcould include a more flexible material such as polyimide, plastic, ortape. Therefore, although the carrier wafer is illustrated as a wafer,embodiments of the are not limited to wafers/substrates and the presentinvention should be understood in a broader context. The carrier wafer701 will provide sufficient rigidity to maintain the integrity ofepitaxial layers during processing operations.

FIG. 5 is a simplified cross-sectional diagram illustrating thinning ofthe handle wafer according to an embodiment of the present invention.Referring to FIG. 5, the structure illustrated in FIG. 4 has beeninverted, with the carrier wafer 701 on the bottom and the handlesubstrate 100 on the top. Additionally, FIG. 5 illustrates partialremoval of the handle substrate using, for example, a thinning,grinding, or other removal process. Although not illustrated in FIG. 5,the bonding layer 101 and the GaN-based seed layer 102 are removed usinga thinning or other removal process to expose the GaN buffer layer 201.Thus, the seed layer, which had provided an epitaxial growth surface forthe GaN buffer layer, is removed in some embodiments once the purpose ofthe seed layer (e.g., providing a high quality (for instancesingle-crystal) epitaxial growth surface) has been accomplished.

The handle substrate can be lapped, ground, or milled during a highremoval rate process and then chemically etched, physically etched, oretched using a combination of chemical and physical etching (e.g., wetetch, CAIBE, dry etching using ICP, RIE, or the like). Similar etchprocesses are then used to remove the bonding layer 101 and the seedlayer 102 to expose the buffer layer 201. Combinations of chemicaletching, lapping, dry etching, and the like can be utilized depending onthe particular materials. Since GaN is resistant to most wet etches,selective etches can be used to remove the bonding layer 101, which caninclude an oxide, nitride, or other suitable material that is removedduring chemical etching in a manner that is selective for the underlyingGaN-based seed layer 102. Thus, a combination of lapping and chemicaletching can be used to remove the handle substrate 100 and the bondinglayer 101 (e.g., bonding oxide) in some embodiments to thereby exposethe GaN seed layer 102. The GaN seed layer can then be removed using adry etch (e.g., ICP) that is suitable for the removal of GaN-basedmaterials, and the GaN buffer layer 201 may be thick enough to allow forprocess margin in the event of over-etching. Depending on the dopingtype and structure of seed layer 102, a wet etch may also be used toremove seed layer 102 without substantially etching buffer layer 201.One of ordinary skill in the art would recognize many variations,modifications, and alternatives.

FIG. 6 is a simplified cross-sectional diagram illustrating removal oflayers and formation of an electrode according to an embodiment of thepresent invention. Comparing FIG. 5 to FIG. 6, the handle substrate, thebonding layer and the seed layer 102 have been removed as describedabove to expose the buffer layer 201 and a bottom electrode 801 has beendeposited to provide for electrical contact to the n+ GaN buffer layer201. In some embodiments, buffer layer 201 provides access to a nitrogenface of the GaN crystal structure after removal of the seed layer.Because the nitrogen face enables formation of good ohmic contacts usinglow temperature metal deposition processes, the formation of the bottomelectrode 801 can be a low temperature process. In some embodiments, thebottom electrode 801 can be deposited at room temperature without theneed for a post-deposition anneal. Various techniques can be used forcontact formation, including metal evaporation, sputtering, plating,combinations thereof, or the like. Referring to FIG. 6, it should benoted that the use low temperature processes for the formation of thebottom electrode 801 enable the use of materials for the sacrificialbonding layer 601 that would not necessarily be available if a hightemperature metallization process was used to form the bottom electrode801. Additional description related to electrodes and metallization isprovided in U.S. patent application Ser. No. 13/552,365, filed on Jul.18, 2012, and entitled “GaN Power Device with Solderable Back Metal,”the disclosure of which is hereby incorporated by reference in itsentirety for all purposes.

FIG. 7 is a simplified cross-sectional diagram illustrating joining of asubstrate according to an embodiment of the present invention. Asillustrated in FIG. 7, a device substrate 1001 (also referred to as anelectrical and thermal substrate because of the properties discussedbelow) is joined to the bottom electrode 801 using a bonding interfacelayer 901. The electrical and thermal substrate 1001 provides electricalconductivity to devices fabricated using the epitaxial layers as well asthermal conductivity to conduct heat away from the active devices. Asexamples, the electrical and thermal substrate 1001 can include avariety of materials including molybdenum, copper, tungsten, similarmetals, metal alloys, combinations thereof, or the like. As describedbelow, the electrical and thermal substrate 1001 also providesmechanical support for the epitaxial device layers after removal of thecarrier wafer 701. The electrical and thermal substrate can be joined tothe illustrated structure using the bonding interface layer inconjunction with or supplemented by a soldering, sintering, or othersuitable process.

As an alternative to the use of an electrical and thermal substrate, thebottom electrode 801 could be formed (e.g., plated) to a sufficientthickness to provide for mechanical support of the epitaxial layers. Forexample, bottom electrode 801 may include copper, nickel, aluminum,similar metals or alloys of several metals. In one embodiment, layer 801may comprise a copper layer of 25 μm to 100 μm thickness formed by achemical and/or electrochemical plating process. In some embodiments,the thickness and composition of top electrode 501 may be similar tobottom electrode 801, such that the mechanical stress caused by themismatch in thermal coefficients of expansion (TCE) of these electrodesand GaN device layers is balanced. Thus, depending on the particularimplementation, the electrical and thermal substrate may be utilized,whereas in other embodiments, alternative techniques are used to providethe desired mechanical, electrical, and thermal performancecharacteristics.

FIG. 8 is a simplified cross-sectional diagram illustrating removal ofthe carrier wafer according to an embodiment of the present invention.As illustrated in FIG. 8, the carrier wafer has been debonded or removedalong with the sacrificial bonding layer to expose the top electrode andportions of the other applicable functional layers. In embodiments inwhich the sacrificial bonding layer includes wax, an organic solvent canbe used to remove this layer. As mentioned above, although an electricaland thermal substrate is illustrated in FIG. 8, this is not required bythe present invention and plating of one or more layers, including extraplating of bottom electrode 801 can be used to provide mechanicalsupport for the device layers. In a particular embodiment, at least oneof the top electrode or the bottom electrode are plated to a sufficientthickness to provide mechanical support, for example 25 μm of copper forthe top electrode and 25 μm of copper for the bottom electrode. In thisparticular embodiment, stress balancing of the top electrode 501 and thebottom electrode 801 can be utilized to place the epitaxial devicelayers in compressive stress.

Utilizing the engineered substrate during the fabrication processresults in a device structure substantially free of substrate materialsince the GaN substrate characterizing conventional devices has beenreplaced with the GaN buffer layer 201, which can be very thin incomparison to a conventional substrate. For example, a bulk GaN wafermay have a starting thickness of 300 μm to 500 μm, depending on thewafer diameter. Because the substrate is in series with the electricalcurrent flow and the heat flow, it adds significantly to both theelectrical and thermal resistance. In conventional vertical power deviceprocessing on bulk substrates, the substrate is preferably thinned toreduce its thermal and electrical resistance. However, the minimum finalsubstrate thickness is limited by handling and mechanical stress issues.In state-of-the-art vertical power devices, the final substratethickness may be in the range of 50 μm to 150 μm. According to theembodiments described herein, the equivalent final “substrate” thicknessis the same as the thickness of N+ GaN buffer layer 301, which may be inthe range of 1 μm to 10 μm. Thus, the present invention providesvertical GaN power devices with much lower electrical and thermalresistance compared to vertical GaN power devices fabricated on bulk GaNsubstrates.

FIG. 9A is a simplified schematic diagram of a GaN Schottky diodestructure according to an embodiment of the present invention. The GaNSchottky diode structure illustrated in FIG. 9A is an example of atwo-terminal GaN-based device that utilizes the epitaxial structurefabricated using the engineered substrate process described herein.Additional description related to Schottky diode structures is providedin U.S. patent application Ser. No. 13/225,345, filed on Sep. 2, 2011and U.S. patent application Ser. No. 13/289,219, filed on Nov. 4, 2011,the disclosures of which are hereby incorporated by reference in theirentirety for all purposes. As illustrated in FIG. 9A, a Schottky contactis formed as the top electrode, providing a Schottky barrier to lightlydoped n-type GaN-based drift layer.

By using an engineered substrate to fabricate the device illustrated inFIG. 9A, as well as other devices described herein, only epitaxialmaterial is present between the bottom electrode and the Schottkycontact. As discussed in relation to the other devices described herein,embodiments of the present invention utilize the engineered substrate toremove the substrate material that is typically present in conventionaldevices. Thus, the buffer layer and the drift layer, in the deviceillustrated in FIG. 9A, are both epitaxial layers that are grown usingthe seed layer, with the seed layer subsequently removed, resulting inonly epitaxial material being present in the layers between thecontacts. Because the device structure is free of substrate material,the material properties are defined by the epitaxial growth processes,which provide more control for device design and fabrication.

The removal of the substrate material enables the fabrication of devicestructures that are thinner than conventional devices, for example, withthe thickness of the buffer layer (i.e., the distance measured from thebottom electrode to the III-nitride drift layer) being less than 5 μm,less than 4 μm, less than 3 μm, less than 2 μm, less than 1 μm, lessthan 0.5 μm, less than 0.1 μm, or the like, which is appropriate for astructure with only a buffer layer between the original seed layer andthe drift layer. Additionally, embodiments of the present inventioncontrast with conventional devices since the III-nitride epitaxiallayers, including the buffer and drift layer, are silicon-doped n-typelayers, rather than being oxygen doped, which is the conventional dopantfor n-type GaN substrates. Thus, the buffer layer utilized in theillustrated devices are characterized by an oxygen concentration lessthan 5×10¹⁷ cm⁻³ (for example, less than 2 x 10¹⁷ cm⁻³), which is anoxygen concentration associated with GaN substrates. Additionally, thesilicon concentration of the buffer layer can be greater than 1×10¹⁸cm⁻³. Thus, devices fabricated using engineered substrates provide lowerelectrical resistance, lower thermal resistance, and the like because ofthe absence of the substrate material.

FIG. 9B is a simplified schematic diagram of a GaN p-n diode structureaccording to an embodiment of the present invention. The GaN p-njunction diode structure illustrated in FIG. 9B is another example of atwo-terminal GaN-based device that utilizes the epitaxial structurefabricated using the engineered substrate process described herein.Additional description related to p-n junction diode structures isprovided in U.S. patent application Ser. No. 13/225,345, filed on Sep.2, 2011 and U.S. patent application Ser. No. 13/289,219, filed on Nov.4, 2011, the disclosures of which are hereby incorporated by referencein their entirety for all purposes. As illustrated in FIG. 9B, a p-typeohmic contact is formed as the top electrode, providing an ohmic contactto p-type GaN-based layer, which forms a p-n junction with lightly dopedn-type GaN-based drift layer.

In addition to Schottky diode and p-n junction diode devices, a mergedPIN, Schottky (MPS) diode structure can be fabricated using engineeredsubstrates as described herein. Additional description related to MPSdiodes is provided in U.S. patent application Ser. No. 13/300,028, filedon Nov. 18, 2011, the disclosure of which is hereby incorporated byreference in its entirety for all purposes.

FIG. 10 is a simplified schematic diagram of a three-terminal GaN FETstructure according to an embodiment of the present invention. Thethree-terminal device illustrated in FIG. 10 is a vertical junctionfield effect transistor (JFET), which can be fabricated using techniquesdiscussed in more detail in U.S. patent application Ser. No. 13/198,655,filed on Aug. 4, 2011, the disclosure of which is hereby incorporated byreference in its entirety for all purposes. As illustrated in FIG. 10,the vertical JFET includes a lightly doped n-type GaN-based drift layer1050 and a lightly doped GaN-based channel region 1051. Gate material1060 (e.g., a p-type GaN-based layer) is biased by application ofvoltage to metal 1061, which forms an ohmic contact to the p-type gatematerial. The source region 1052 is biased by application of voltage tosource metal 1053, which forms an ohmic contact to the heavily dopedn-type source region. Because the structure illustrated in FIG. 10utilized an engineered substrate during fabrication, voltage dropassociated with a GaN substrate is reduced since the bottom electrode isconnected to the heavily doped n-type GaN buffer layer and the driftlayer 1050.

FIG. 11 is a simplified schematic diagram of a three-terminal GaNbipolar structure according to an embodiment of the present invention.Referring to FIG. 11, the functional layers include a heavily dopedp-type base 1151 positioned between a lightly doped n-type drift layer1150 connected to the bottom electrode 801 (collector) and a heavilydoped emitter structure including an n-type Al_(x)Ga_(1−x)N layer 1160,an n-type GaN layer 1161, and an ohmic metal contact 1162 (emitter) tothe n-type GaN layer 1161. Current entering the base 1151, biased usingan ohmic contact 1152 to the p-GaN layer is amplified to produce thecollector and emitter current. Although an NPN BJT is illustrated inFIG. 11, this is not required by the present invention and PNP designscan be utilized as well. Doping and thickness of the various layers ofthe BJT are selected to provide predetermined device characteristicsappropriate to the particular design. One of ordinary skill in the artwould recognize many variations, modifications, and alternatives.

FIG. 12 is a simplified schematic diagram illustrating device bondingaccording to an embodiment of the present invention. FIG. 12 presents analternative design to the use of an electrical and thermal substrate asillustrated in FIG. 8. As illustrated in FIG. 12, the GaN buffer layer201, the GaN drift layer 301, the other applicable functional layers401, and the top electrodes (#1 and #2) are illustrated and can becompared to these layers in FIG. 3. Multiple top electrodes 1201 and1202 are fabricated in the embodiment illustrated in FIG. 12. Thestructure is then flip-chip bonded to substrate 1220 using bonds 1210.Thus, flip-chip bonding can be used after the formation of thefunctional layers to bond the structure to substrate 1220. Removal ofthe handle substrate 100 along with bonding layer and the seed layer isthen performed prior to formation of the bottom electrode 1230.

In some embodiments using three-terminal devices, substrate 1220 caninclude wire traces and/or insulated interconnects connected to bondingregions to provide separate electrical circuits for a first topelectrode 1201 and a second top electrode 1202. An example is a designusing direct bonded copper (DBC). The top electrodes can be formed usingplating as described above. Thus, using the design illustrated in FIG.12, both electrical contact to the substrate as well as thermalconduction to remove device heat can be provided by the substrate.

FIG. 13 is a simplified flowchart illustrating a method of fabricatingan electronic device according to an embodiment of the presentinvention. The method 1300 includes providing an engineered substratestructure comprising a III-nitride seed layer (1310) and formingGaN-based functional layers coupled to the III-nitride seed layer. In anembodiment, the III-nitride seed layer includes GaN material, such as aportion of a GaN substrate removed during a layer transfer process, forexample, an n-type GaN-based material. In some embodiments, the methodincludes epitaxially growing a III-nitride buffer layer coupled to theIII-nitride seed layer and a III-nitride drift layer coupled to theIII-nitride buffer layer. In these embodiments, the method canadditionally include epitaxially growing the GaN-based functional layersin order to form the GaN-based functional layers.

The method also includes forming a first electrode structureelectrically coupled to at least a portion of the GaN-based functionallayers (1314) and joining a carrier substrate opposing the GaN-basedfunctional layers (1316).

Joining the carrier wafer to the GaN-based functional layers can includeforming an electrode structure coupled to at least a portion of one ofthe GaN-based functional layers, forming a sacrificial bonding layercoupled to another portion of the one of the GaN-based functional layersand at least a portion of the electrode structure, and bonding thecarrier wafer to the sacrificial bonding layer.

The method further includes removing at least a portion of theengineered substrate structure (1318) and forming a second electrodestructure electrically coupled to at least another portion of theGaN-based functional layers (1320). Additionally, the method includesremoving the carrier substrate (1322). In a particular embodiment,removing the carrier substrate includes removing the sacrificial bondinglayer discussed above. As described herein, the engineered substrate caninclude a handle wafer and a bonding layer coupled to the III-nitrideseed layer. In this embodiment, removing at least a portion of theengineered substrate structure can include mechanically removing thehandle wafer, chemically etching the bonding layer, and physicallyetching the III-nitride seed layer. Thus, embodiments provide structuresthat are substantially free from substrate materials, rather usingepitaxially grown materials to form the device layers.

In some embodiments, the method can also include joining a devicesubstrate to the second electrode prior to removing the carriersubstrate, whereas in other embodiments, the second electrode is platedto a thickness such that a device substrate is not utilized, with thestructure of the second electrode providing sufficient mechanicalsupport for other layers during fabrication and packaging processes.

It should be appreciated that the specific steps illustrated in FIG. 13provide a particular method of fabricating an electronic deviceaccording to an embodiment of the present invention. Other sequences ofsteps may also be performed according to alternative embodiments. Forexample, alternative embodiments of the present invention may performthe steps outlined above in a different order. Moreover, the individualsteps illustrated in FIG. 13 may include multiple sub-steps that may beperformed in various sequences as appropriate to the individual step.Furthermore, additional steps may be added or removed depending on theparticular applications. One of ordinary skill in the art wouldrecognize many variations, modifications, and alternatives.

It is also understood that the examples and embodiments described hereinare for illustrative purposes only and that various modifications orchanges in light thereof will be suggested to persons skilled in the artand are to be included within the spirit and purview of this applicationand scope of the appended claims.

What is claimed is:
 1. A method for fabricating an electronic device,the method comprising: providing an engineered substrate structurecomprising a III-nitride seed layer; forming GaN-based functional layerscoupled to the III-nitride seed layer; forming a first electrodestructure electrically coupled to at least a portion of the GaN-basedfunctional layers; joining a carrier substrate opposing the GaN-basedfunctional layers; removing at least a portion of the engineeredsubstrate structure; forming a second electrode structure electricallycoupled to at least another portion of the GaN-based functional layers;and removing the carrier substrate.
 2. The method of claim 1 furthercomprising joining a device substrate to the second electrode prior toremoving the carrier substrate.
 3. The method of claim 1 wherein theIII-nitride seed layer comprises a GaN material.
 4. The method of claim1 wherein the III-nitride seed layer comprises an n-type GaN-basedmaterial.
 5. The method of claim 1 further comprising epitaxiallygrowing a III-nitride buffer layer coupled to the III-nitride seed layerand a III-nitride drift layer coupled to the III-nitride buffer layer.6. The method of claim 5 wherein forming GaN-based functional layerscomprises epitaxially growing the GaN-based functional layers.
 7. Themethod of claim 1 wherein joining the carrier wafer to the GaN-basedfunctional layers comprises: forming an electrode structure coupled toat least a portion of one of the GaN-based functional layers; forming asacrificial bonding layer coupled to another portion of the one of theGaN-based functional layers and at least a portion of the electrodestructure; and bonding the carrier wafer to the sacrificial bondinglayer.
 8. The method of claim 7 wherein removing the carrier substratecomprises removing the sacrificial bonding layer.
 9. The method of claim1 wherein the engineered substrate comprises a handle wafer and abonding layer coupled to the III-nitride seed layer, and whereinremoving at least a portion of the engineered substrate structurecomprises mechanically removing the handle wafer, chemically etching thebonding layer, and physically etching the III-nitride seed layer.